Method of forming integrated circuitry, method of forming a contact opening, and integrated circuitry

ABSTRACT

A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.

TECHNICAL FIELD

[0001] This invention relates to methods of forming integrated circuitry, to methods of forming contact openings, and to integrated circuitry.

BACKGROUND OF THE INVENTION

[0002] Semiconductor processing often involves the deposition of films or layers over or on a semiconductor substrate surface which may or may not have other layers already formed thereon. In typical circuitry fabrication, portions of an outer layer are masked, typically using photoresist, to provide a desired pattern over the outer layer. An underlying layer is then removed by chemical etching through the mask opening, with the mask covering and protecting other areas from the etching. Often it is desirable to etch an outer layer or layers selectively relative to an underlying layer. Accordingly, materials on the substrate, etch chemistry and conditions are continually being developed and improved to achieve a manner by which the desired layer(s) can be etched while stopping and substantially not etching an underlying layer.

[0003] Also, some layers are removed by mechanical polishing action or by chemical mechanical polishing action. In many such instances, it is also desirable to remove one or more layers while stopping on some immediately underlying layer.

SUMMARY

[0004] The invention includes methods of forming integrated circuitry, methods of forming contact openings, and integrated circuitry. In one implementation, a silicon nitride comprising layer is formed over a semiconductor substrate. The silicon nitride comprising layer includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate the silicon nitride comprising layer. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal.

[0005] In one implementation, a substantially undoped silicon dioxide comprising layer is formed over a semiconductor substrate. The substantially undoped silicon dioxide comprising layer includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate the substantially undoped silicon dioxide comprising layer. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal.

[0006] In one implementation, integrated circuitry includes a pair of spaced conductive device components received over a substrate, with such at least partially defining a node location there between. Each device component has at least one sidewall which faces the other device component of the pair. An insulative material mass is received over each of the sidewalls. The masses are laterally spaced from one another in a non-contacting relationship. The masses comprise a first insulative material comprising B, Al, Ga or mixtures thereof. A conductive contact is received between the insulative material masses in electrical connection with the node location.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

[0008]FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment in process in accordance with an aspect of the invention.

[0009]FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1.

[0010]FIG. 3 is a view of the FIG. 1 wafer fragment at an alternate processing step to that shown by FIG. 2.

[0011]FIG. 4 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 2.

[0012]FIG. 5 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 4.

[0013]FIG. 6 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 5.

[0014]FIG. 7 is a diagrammatic sectional view of an alternate embodiment semiconductor wafer fragment in process in accordance with an aspect of the invention.

[0015]FIG. 8 is a view of the FIG. 7 wafer fragment at a processing step subsequent to that shown by FIG. 7.

[0016]FIG. 9 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 8.

[0017]FIG. 10 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 9.

[0018]FIG. 11 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 10.

[0019]FIG. 12 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 11.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

[0021] Exemplary preferred embodiments of forming integrated circuitry are initially described with reference to FIGS. 1-6. FIG. 1 depicts a wafer fragment 10 comprising a bulk monocrystalline silicon substrate region 12. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated.

[0022] A pad oxide layer 14 is formed over semiconductor substrate 12. A silicon nitride comprising layer 16 is formed over pad oxide layer 14 and semiconductor substrate 12. An exemplary thickness range for layer 14 is from 50 Angstroms to 150 Angstroms, while an exemplary thickness range for layer 16 is from 400 Angstroms to 1200 Angstroms. Silicon nitride comprising layer 16 has an outer surface 18.

[0023] Referring to FIG. 2, at least one enriched region 20 is formed within silicon nitride comprising layer 16. Enriched region 20 is characterized at least by the presence of Al, Ga or mixture thereof. One preferred method of forming enriched region 20 is by ion implanting at least one of Al and Ga into silicon nitride comprising layer 16. Another preferred method is by plasma enhanced or gas phase thermal diffusion. An exemplary diffusion species for aluminum is trimethyl aluminum, while an exemplary diffusion species for gallium is trimethyl gallium. Preferably, enriched region 20 extends to at least a portion of outer surface 18, with FIG. 2 depicting region 20 extending to all of outer surface 20. An example preferred implant is to place a peak concentration depth from about 10 Angstroms to about 400 Angstroms beneath outer surface 18. Again, trimethyl aluminum and trimethyl gallim would be exemplary implant species. Exemplary doses are from 5×10¹² ions/cm² to 15×10¹² ions/cm², with a narrower preferred range being from 10×10¹² ions/cm² to 12×10¹² ions/cm². Exemplary implant energies are from 2 KeV to 25 Kev. FIG. 3 depicts an alternate preferred embodiment wafer fragment 10 a whereby enriched region 20 a is spaced from outer surface 18. Of course, regions 20 and 20 a might also be formed by methods other than ion implanting or gas phase diffusion, for example and by way of example only such as during the deposition of layer 16 (i.e., during chemical vapor deposition) or by deposition of a separate layer thereover. For example, and by way of example only, the forming of said silicon nitride comprising layer might comprise chemical vapor deposition over a previously deposited layer consisting essentially of silicon nitride.

[0024] Referring to FIG. 4, layers 16 and 14 have been patterned to form an opening 22 therethrough and into semiconductor substrate 12.

[0025] Referring to FIG. 5, a silicon dioxide comprising layer 24 is formed proximate silicon nitride comprising layer 16 and, in the preferred embodiment as shown, is formed on (in contact with) silicon nitride comprising layer 16. Silicon dioxide comprising layer 24 might be doped or substantially undoped. In the context of this document, “doped” means doping with one or both of phosphorous and boron, and to a total dopant concentration of one or more of such materials to at least 1% by weight average. “Substantially undoped” means a total combined doping of boron and/or phosphorous, if any, at less than 1% by weight.

[0026] Referring to FIG. 6, silicon dioxide comprising layer 24 is removed substantially selectively relative to silicon nitride comprising layer 16, with the at least one enriched region 20 preferably enhancing selectivity to silicon nitride comprising layer 16 during the removing. Such removing is preferably by chemical etching, or by other techniques for example by polishing. In the context of this document, “substantially selectively” means a removal rate of one material relative to another of at least 1.5:1. By way of example only, an exemplary process for etching silicon dioxide selectively relative to silicon nitride where region 20 facilitates selectivity in the etch include an TEL DRM reactive ion etcher, operated at 1500 W, 45 mtorr, Ar flow at 500 sccm, C₄F₈ flow at 12 sccm, and CH₂F₂ flow at 6 sccm.

[0027] Regions 20/20 a might, of course, in the depicted first exemplary embodiment, be formed prior to or subsequent to fabrication of the exemplary opening 22. Further, in one preferred embodiment, silicon nitride comprising layer 16 with implanted region 20/20 a can be annealed prior to the removing action. Such might be desirable to facilitate migration of the gallium or aluminum to bond sites within silicon nitride comprising layer 16. Any alternate or additional fabrication is also contemplated in the context of the accompanying claims.

[0028] In one implementation, the invention also contemplates forming integrated circuitry comprising forming a substantially undoped silicon dioxide comprising layer over a semiconductor substrate. At least one enriched region analogous to regions 20 and 20 a in the above-described first preferred silicon nitride comprising layer embodiment is formed within the substantially undoped silicon dioxide comprising layer. The enriched region comprises B, Al, Ga or mixtures thereof. An exemplary diffusion species for Boron is diborane, while an exemplary implant species for boron is B¹¹. A doped silicon dioxide comprising layer is formed proximate, and more preferably on, the substantially undoped silicon dioxide comprising layer. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer. The at least one enriched region preferably enhances selectivity to the substantially undoped silicon dioxide comprising layer during the removing. Again, removing is preferably by chemical etching, with removal by polishing or other techniques also of course being contemplated. By way of example only, an exemplary process for etching doped silicon dioxide selectively relative to substantially undoped silicon dioxide where region 20 facilitates selectivity in the etch include a 12 Liter Applied Materials 5000 Etch Chamber, operated at 1000 W, 50 mTorr, Ar flow at 120 sccm, CF₄ flow at 30 sccm, CHF₃ flow at 50 sccm, and CH₂F₂ flow at 15 sccm.

[0029] The above-described preferred embodiments are associated with forming respective enriched regions within the subject layers. However, in one aspect, the invention also more generically contemplates forming a silicon nitride comprising layer also comprising Al, Ga or a mixture thereof. Such Al, Ga or a mixture thereof might be present in the silicon nitride comprising layer as an enriched region, as described in the above preferred embodiments, or such might be substantially homogeneously distributed within the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the subject removing.

[0030] With respect to a substantially undoped silicon dioxide comprising layer, the invention also more generically contemplates B, Al, Ga or mixtures thereof being present within the substantially undoped silicon dioxide comprising layer, with such enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removing. Again by way of example only, the B, Al, Ga or mixtures thereof might be present as an enriched region or portion thereof, or might be substantially homogeneously distributed within the substantially undoped silicon dioxide comprising layer.

[0031] By way of example only, alternate preferred embodiments of the invention are described with reference to FIGS. 7-12. FIG. 7 depicts a semiconductor wafer fragment 40 comprising a bulk monocrystalline silicon substrate 42. A pair of field effect transistor gate stacks 44 and 46 are shown formed over substrate 42. Such respectively comprise a gate dielectric layer 48, a conductive polysilicon portion 50, an overlying higher conductive silicide layer 52, and an overlying insulative cap 54. Regions 50 and 52 constitute the conductive portion of stacks 44 and 46, and depict an exemplary pair of spaced conductive device components formed over semiconductor substrate 42. Of course, any alternate pair of spaced conductive device components are contemplated. For purposes of the continuing discussion, spaced conductive device components 50/52 have at least one sidewall 56 which faces the other device component of the pair. This particular preferred embodiment is described in conjunction with a method of forming a contact opening within insulative material to a node location, for example location 60, located between conductive device components 50/52 of each stack 44 and 46.

[0032] Referring to FIG. 8, an insulative layer 62 is formed over device components 50/52 and on substrate material 42 between the device components. In one preferred embodiment, layer 62 comprises silicon nitride. In another preferred exemplary embodiment, insulative layer 62 comprises substantially undoped silicon dioxide. In the depicted preferred embodiment, a continuous enriched outer region 64 comprising B, Al, Ga or mixtures thereof is formed. Exemplary techniques for forming the same include those as described above. Preferably as shown, outer region 64 is formed to be continuous, and also to extend to at least a portion of, and to the entirety of as shown, the outer surfaces of insulative layer 62.

[0033] Referring to FIG. 9, layer 62 has been anisotropically etched, preferably without any photomasking, effective to form insulative material masses 66, 68, 70 and 72 in the form of insulative spacers, with insulative masses 68 and 70 being formed over facing sidewalls 56 of conductive device components 50/52. Such insulative material masses have lateral outer surfaces 74 extending from bases thereof proximate substrate 42 to the tops of the illustrated constructions. Spacers 66, 68, 70 and 72 also comprise respective enriched lateral outer regions 76 comprising B, Al, Ga or mixtures thereof. Such provides but one example of forming insulative material masses over each of sidewalls 56, with the preferred masses being laterally spaced from one another in a non-contacting relationship. Any alternate existing or yet-to-be-developed method of forming insulative masses is also contemplated. In the depicted preferred embodiment, enriched lateral outer regions 76 extend to at least a portion of the respective outer lateral surfaces 74, and are elevationally spaced from substrate material 42 between the device components.

[0034] Referring to FIG. 10, a second insulative material 80, different from the first insulative material, is formed between insulative material masses 68 and 70, and otherwise preferably over the substrate as shown. Where insulative masses 68 and 70 comprise substantially undoped silicon dioxide, one preferred material for layer 80 is doped silicon dioxide. Where insulative masses 68 and 70 comprise silicon nitride, two exemplary materials for layer 80 include doped silicon dioxide and substantially undoped silicon dioxide.

[0035] Referring to FIG. 11, a contact opening 82 is etched into insulative material 80 to node location 60 between insulative material masses 68, 70 substantially selectively relative thereto. Lateral outer enriched regions 76 preferably enhance selectivity to the insulative masses during such etching. In a more generic sense, the invention contemplates inclusion of B, Al, Ga or mixtures thereof within insulative material masses 68, 70 whether in enriched regions 76 as shown, substantially homogeneously distributed within the insulative material masses, or otherwise.

[0036] Referring to FIG. 12, conductive material 86 is shown having been formed within contact opening 82 between insulative material masses 68 and 70 in electrical connection with node location 60. Such might be provided by the provision of one or more conductive layers which, in the preferred embodiment, shows the formation of a conductive contact to a node location 60. Node location 60 might be a diffusion region, or any node location constituting a portion of integrated circuitry being formed.

[0037] The above-described preferred embodiments are only exemplary in connection with methodical aspects of the invention, which are only limited by the accompanying claims as literally worded and as interpreted in accordance with the doctrine of equivalents. The invention also contemplates integrated circuitry independent of the method of fabrication as literally claimed without limitation to the preferred depicted embodiments, and as interpreted in accordance with the doctrine of equivalents.

[0038] In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. 

1. A method of forming integrated circuitry comprising: forming a silicon nitride comprising layer over a semiconductor substrate; forming at least one enriched region within the silicon nitride comprising layer, the enriched region comprising Al, Ga or a mixture thereof; forming a silicon dioxide comprising layer proximate the silicon nitride comprising layer; and removing the silicon dioxide comprising layer substantially selectively relative to the silicon nitride comprising layer, the at least one enriched region enhancing selectivity to the silicon nitride comprising layer during the removing.
 2. The method of claim 1 wherein the silicon nitride comprising layer has an outer surface, the enriched region extending to at least a portion of the outer surface.
 3. The method of claim 1 wherein the silicon nitride comprising layer has an outer surface, the enriched region being spaced from the outer surface.
 4. The method of claim 1 wherein the enriched region comprises Al.
 5. The method of claim 1 wherein the enriched region comprises Ga.
 6. The method of claim 1 wherein the enriched region comprises Al and Ga.
 7. The method of claim 1 further comprising annealing the silicon nitride comprising layer prior to the removing.
 8. The method of claim 1 wherein the silicon dioxide comprising layer is formed on the silicon nitride comprising layer.
 9. The method of claim 1 wherein the silicon dioxide comprising layer is substantially undoped.
 10. The method of claim 1 wherein the silicon dioxide comprising layer is doped.
 11. The method of claim 1 wherein the removing comprises etching.
 12. A method of forming integrated circuitry comprising: forming a silicon nitride comprising layer over a semiconductor substrate; implanting at least one of Al and Ga into the silicon nitride comprising layer; forming a silicon dioxide comprising layer proximate the silicon nitride comprising layer; and removing the silicon dioxide comprising layer substantially selectively relative to the silicon nitride comprising layer, the implanted at least one of Al and Ga enhancing selectivity to the silicon nitride comprising layer during the removing.
 13. The method of claim 12 comprising implanting Al.
 14. The method of claim 12 comprising implanting Ga.
 15. The method of claim 12 wherein the silicon nitride comprising layer has an outer surface, the implanting forming an implanted region which extends to at least a portion of the outer surface.
 16. The method of claim 12 wherein the silicon nitride comprising layer has an outer surface, the implanting forming an implanted region which is spaced from the outer surface.
 17. A method of forming integrated circuitry comprising: forming a substantially undoped silicon dioxide comprising layer over a semiconductor substrate; forming at least one enriched region within the substantially undoped silicon dioxide comprising layer, the enriched region comprising B, Al, Ga or mixtures thereof; forming a doped silicon dioxide comprising layer proximate the substantially undoped silicon dioxide comprising layer; and removing the doped silicon dioxide comprising layer substantially selectively relative to the substantially undoped silicon dioxide comprising layer, the at least one enriched region enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removing.
 18. The method of claim 17 wherein the enriched region comprises B.
 19. The method of claim 17 wherein the enriched region comprises Al.
 20. The method of claim 17 wherein the enriched region comprises Ga.
 21. The method of claim 17 wherein the enriched region comprises at least two of B, Al, and Ga.
 22. The method of claim 17 wherein the enriched region comprises B, Al, and Ga.
 23. The method of claim 17 wherein the doped silicon dioxide is formed on the substantially undoped silicon dioxide.
 24. The method of claim 17 wherein the substantially undoped silicon dioxide comprising layer has an outer surface, the enriched region extending to at least a portion of the outer surface.
 25. The method of claim 17 wherein the substantially undoped silicon dioxide comprising layer has an outer surface, the enriched region being spaced from the outer surface.
 26. The method of claim 17 wherein the removing comprises etching.
 27. A method of forming integrated circuitry comprising: forming a substantially undoped silicon dioxide comprising layer over a semiconductor substrate; implanting at least one of B, Al, and Ga into the substantially undoped silicon dioxide comprising layer; forming a doped silicon dioxide comprising layer proximate the substantially undoped silicon dioxide comprising layer; and removing the doped silicon dioxide comprising layer substantially selectively relative to the substantially undoped silicon dioxide comprising layer, the implanted at least one of B, Al and Ga enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removing.
 28. The method of claim 27 comprising implanting B.
 29. The method of claim 27 comprising implanting Al.
 30. The method of claim 27 comprising implanting Ga.
 31. The method of claim 27 wherein the substantially undoped silicon dioxide comprising layer has an outer surface, the implanting forming an implanted region which extends to at least a portion of the outer surface.
 32. The method of claim 27 wherein the substantially undoped silicon dioxide comprising layer has an outer surface, the implanting forming an implanted region which is spaced from the outer surface.
 33. A method of forming a contact opening within insulative material to a node location between a pair of conductive device components, comprising: forming a pair of spaced conductive device components over a semiconductor substrate, each device component having at least one sidewall which faces the other device component of the pair; forming an insulative material mass over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising a first insulative material and having a respective lateral outer enriched region comprising B, Al, Ga or mixtures thereof; forming a second insulative material different from the first insulative material between the insulative material masses; and etching a contact opening into the second insulative material to a node location between the insulative material masses substantially selectively relative to the insulative material masses, the lateral outer enriched regions enhancing selectivity to the insulative masses during the etching.
 34. The method of claim 33 wherein the device components comprise transistor gates.
 35. The method of claim 33 wherein the forming of the insulative material masses comprises depositing the first insulative material and anisotropically etching it to form insulative sidewall spacers over each of the sidewalls.
 36. The method of claim 33 wherein the enriched region comprises B.
 37. The method of claim 33 wherein the enriched region comprises Al.
 38. The method of claim 33 wherein the enriched region comprises Ga.
 39. The method of claim 33 wherein the first material comprises silicon nitride and the second material comprises silicon dioxide.
 40. The method of claim 39 wherein the silicon dioxide is doped.
 41. The method of claim 33 wherein the first material comprises substantially undoped silicon dioxide and the second material comprises doped silicon dioxide.
 42. The method of claim 33 wherein the insulative masses comprise respective outer surfaces the enriched regions extending to at least a portion of the respective outer surfaces.
 43. A method of forming a contact opening within insulative material to a node location between a pair of conductive device components, comprising: forming a pair of spaced conductive device components over a semiconductor substrate, each device component having at least one sidewall which faces the other device component of the pair; forming a silicon nitride comprising layer over the device components and on substrate material between the device components, the silicon nitride comprising layer having a continuous enriched outer region comprising B, Al, Ga or mixtures thereof; anisotropically etching the silicon nitride comprising layer effective to form insulative spacers over the facing sidewalls of the components, the spacers comprising enriched lateral outer regions of the silicon nitride comprising layer which are elevationally spaced from the substrate material between the device components. forming an insulative material between the spacers; and etching a contact opening into the insulative material to a node location between the spacers substantially selectively relative to the spacers, the spacer outer enriched regions enhancing selectivity to the spacers during the etching.
 44. The method of claim 43 wherein the insulative masses comprise respective lateral outer surfaces, the enriched regions extending to at least a portion of the respective lateral outer surfaces.
 45. The method of claim 43 wherein the insulative material comprises substantially undoped silicon dioxide.
 46. The method of claim 43 wherein the insulative material comprises doped silicon dioxide.
 47. The method of claim 43 wherein the enriched region comprises B.
 48. The method of claim 43 wherein the enriched region comprises Al.
 49. The method of claim 43 wherein the enriched region comprises Ga.
 50. A method of forming integrated circuitry comprising: forming a silicon nitride comprising layer over a semiconductor substrate, the silicon nitride comprising layer comprising Al, Ga or a mixture thereof; forming a silicon dioxide comprising layer proximate the silicon nitride comprising layer; and removing the silicon dioxide comprising layer substantially selectively relative to the silicon nitride comprising layer, the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removing.
 51. The method of claim 50 wherein the Al, Ga or mixture thereof is substantially homogeneously distributed within the silicon nitride comprising layer.
 52. The method of claim 50 wherein the silicon nitride comprising layer comprises Al.
 53. The method of claim 50 wherein the silicon nitride comprising layer comprises Ga.
 54. The method of claim 50 wherein the silicon nitride comprising layer comprises Al and Ga.
 55. The method of claim 50 wherein the removing comprises etching.
 56. The method of claim 50 wherein the forming of said silicon nitride comprising layer comprises chemical vapor deposition over a previously deposited layer consisting essentially of silicon nitride.
 57. A method of forming integrated circuitry comprising: forming a substantially undoped silicon dioxide comprising layer over a semiconductor substrate, the substantially undoped silicon dioxide comprising layer comprising B, Al, Ga or mixtures thereof; forming a doped silicon dioxide comprising layer proximate the substantially undoped silicon dioxide comprising layer; and removing the doped silicon dioxide comprising layer substantially selectively relative to the substantially undoped silicon dioxide comprising layer, the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removing.
 58. The method of claim 57 wherein the B, Al, Ga or mixtures thereof is substantially homogeneously distributed within the substantially undoped silicon dioxide comprising layer.
 59. The method of claim 57 wherein the substantially undoped silicon dioxide comprising layer comprises B.
 60. The method of claim 57 wherein the substantially undoped silicon dioxide comprising layer comprises Al.
 61. The method of claim 57 wherein the substantially undoped silicon dioxide comprising layer comprises Ga.
 62. The method of claim 57 wherein the removing comprises etching.
 63. The method of claim 57 wherein the forming of the substantially undoped silicon dioxide layer comprises chemical vapor deposition of said layer.
 64. A method of forming a contact opening within insulative material to a node location between a pair of conductive device components, comprising: forming a pair of spaced conductive device components over a semiconductor substrate, each device component having at least one sidewall which faces the other device component of the pair; forming insulative material masses over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising a first insulative material comprising B, Al, Ga or mixtures thereof; forming a second insulative material different from the first insulative material between the insulative material masses; and etching a contact opening to a node location between the insulative material masses substantially selectively relative to the insulative material masses, the B, Al, Ga or mixtures thereof enhancing selectivity to the insulative masses during the etching.
 65. The method of claim 64 wherein the B, Al, Ga or mixtures thereof is substantially homogeneously distributed within the insulative material masses.
 66. The method of claim 64 wherein the insulative masses comprise B.
 67. The method of claim 64 wherein the insulative masses comprise Al.
 68. The method of claim 64 wherein the insulative masses comprise Ga.
 69. Integrated circuitry comprising: a pair of spaced conductive device components received over a substrate, and at least partially defining a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair; an insulative material mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising a first insulative material comprising B, Al, Ga or mixtures thereof; and a conductive contact received between the insulative material masses in electrical connection with the node location.
 70. The integrated circuitry of claim 69 wherein the B, Al, Ga or mixtures thereof is substantially homogeneously distributed within the insulative material masses.
 71. The integrated circuitry of claim 69 wherein the enriched region comprises B.
 72. The integrated circuitry of claim 69 wherein the enriched region comprises Al.
 73. The integrated circuitry of claim 69 wherein the enriched region comprises Ga.
 74. The integrated circuitry of claim 69 wherein the enriched region comprises at least two of B, Al, and Ga.
 75. The integrated circuitry of claim 69 wherein the enriched region comprises B, Al, and Ga.
 76. Integrated circuitry comprising: a pair of spaced conductive device components received over a substrate, and at least partially defining a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair; an insulative material mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising a first insulative material and having a respective lateral outer enriched region comprising B, Al, Ga or mixtures thereof; and a conductive contact received between the insulative material masses in electrical connection with the node location.
 77. The integrated circuitry of claim 76 wherein the device components comprise field effect transistor gates.
 78. The integrated circuitry of claim 76 wherein the insulative material masses comprise anisotropically etched sidewall spacers.
 79. The integrated circuitry of claim 76 wherein the insulative masses comprise bases and tops, the bases being wider than the tops.
 80. The integrated circuitry of claim 76 wherein the insulative material masses have lateral outer surfaces, the outer enriched regions extending to at least a portion of the lateral outer surfaces.
 81. The integrated circuitry of claim 76 wherein the first insulative material comprises substantially undoped silicon dioxide.
 82. The integrated circuitry of claim 76 wherein the first insulative material comprises silicon nitride.
 83. The integrated circuitry of claim 76 wherein the conductive contact is received on the insulative material masses.
 84. The integrated circuitry of claim 76 wherein the enriched region comprises B.
 85. The integrated circuitry of claim 76 wherein the enriched region comprises Al.
 86. The integrated circuitry of claim 76 wherein the enriched region comprises Ga.
 87. The integrat ed circuitry of claim 76 wherein the enriched region comprises at least two of B, Al, and Ga.
 88. The integrated circuitry of claim 76 wherein the enriched region comprises B, Al, and Ga. 